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  • Open Access


    Design and Analysis of 4-bit 1.2GS/s Low Power CMOS Clocked Flash ADC

    G. Prathiba1,*, M. Santhi2

    Intelligent Automation & Soft Computing, Vol.31, No.3, pp. 1611-1626, 2022, DOI:10.32604/iasc.2022.018975

    Abstract High-quality, high-resolution flash ADCs are used in reliable VLSI (Very Large-Scale Integrated) circuits to minimize the power consumption. An analogue electrical signal is converted into a discrete-valued sequence by these ADCs. This paper proposes a four-bit 1.2GS/s low-power Clocked Flash ADC (C-FADC). A low-power Clocked-Improved Threshold Inverter Quantization (CITIQ) comparator, an Adaptive Bubble Free (ABF) logic circuit, and a compact Binary Encoder (BE) are all part of the presented structure. A clock network in the comparator circuit reduces skew and jitters, while an ABF logic circuit detects and corrects fourth order bubble faults detected from thermometer code, and then the… More >

  • Open Access


    An Overview of the Miniaturization and Endurance for Wearable Devices

    Zhoulei Cao1, Qijun Wen1, Xiaoliang Wang1,*, Qing Yang1, Frank Jiang2

    Journal on Internet of Things, Vol.3, No.1, pp. 11-17, 2021, DOI:10.32604/jiot.2021.010404

    Abstract The miniaturization and endurance of wearable devices have been the research direction for a long time. With the development of nanotechnology and the emergence of microelectronics products, people have explored many new strategies that may be applied to wearable devices. In this overview, we will summarize the recent research of wearable devices in these two directions, and summarize some available related technologies. More >

  • Open Access


    A Two-Dimension Time-Domain Comparator for Low Power SAR ADCs

    Liangbo Xie1, *, Sheng Li1, Yan Ren1, Zhengwen Huang2

    CMC-Computers, Materials & Continua, Vol.65, No.2, pp. 1519-1529, 2020, DOI:10.32604/cmc.2020.011701

    Abstract This paper presents a two-dimension time-domain comparator suitable for low power successive-approximation register (SAR) analog-to-digital converters (ADCs). The proposed two-dimension time-domain comparator consists of a ring oscillator collapsebased comparator and a counter. The propagation delay of a voltage controlled ring oscillator depends on the input. Thus, the comparator can automatically change the comparison time according to its input difference, which can adjust the power consumption of the comparator dynamically without any control logic. And a counter is utilized to count the cycle needed to finish a comparison when the input difference is small. Thus, the proposed comparator can not only… More >

  • Open Access


    High Speed Network Intrusion Detection System (NIDS) Using Low Power Precomputation Based Content Addressable Memory

    R. Mythili1, *, P. Kalpana2

    CMC-Computers, Materials & Continua, Vol.62, No.3, pp. 1097-1107, 2020, DOI:10.32604/cmc.2020.08396

    Abstract NIDS (Network Intrusion Detection Systems) plays a vital role in security threats to computers and networks. With the onset of gigabit networks, hardware-based Intrusion Detection System gains popularity because of its high performance when compared to the software-based NIDS. The software-based system limits parallel execution, which in turn confines the performance of a modern network. This paper presents a signature-based lookup technique using reconfigurable hardware. Content Addressable Memory (CAM) is used as a lookup table architecture to improve the speed instead of search algorithms. To minimize the power and to increase the speed, precomputation based CAM (PBCAM) can be used,… More >

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