Arindam Banerjee^1,*, Aniruddha Ghosh², Mainuck Das²

Journal of Quantum Computing, Vol.4, No.3, pp. 121-133, 2022, DOI:10.32604/jqc.2022.034059

Abstract In this paper, focus has been given to design and implement signed binary subtraction in quantum logic. Since the type of operand may be positive or negative, therefore a novel algorithm has been developed to detect the type of operand and as per the selection of the type of operands, separate design techniques have been developed to make the circuit compact and work very efficiently. Two separate methods have been shown in the paper to perform the signed subtraction. The results show promising for the second method in respect of ancillary input count and garbage output count but at the… More >

Marwa A. Elmenyawi^1,2,*, Radwa M. Tawfeek¹

Computer Systems Science and Engineering, Vol.46, No.2, pp. 1827-1844, 2023, DOI:10.32604/csse.2023.036474

Abstract One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design is mandatory for efficient computing systems. In designing low-energy dissipation circuits, reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity. This paper introduces an efficient signed/unsigned 4 × 4 reversible Vedic multiplier with minimum quantum cost. The Vedic multiplier is considered fast as it generates all partial product and their sum in one step. This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output. First, the unsigned Vedic multiplier is designed based on… More >

S. Sharmila Devi^1,*, V. Bhanumathi²

CMC-Computers, Materials & Continua, Vol.70, No.2, pp. 3609-3624, 2022, DOI:10.32604/cmc.2022.020426

Abstract Now a days, MOS Current Mode Logic (MCML) has emerged as a better alternative to Complementary Metal Oxide Semiconductor (CMOS) logic in digital circuits. Recent works have only traditional logic gates that have issues with information loss. Reversible logic is incorporated with MOS Current Mode Logic (MCML) in this proposed work to solve this problem, which is used for multiplier design, D Flip-Flop (DFF) and register. The minimization of power and area is the main aim of the work. In reversible logic, the count of outputs and inputs is retained as the same value for creating one-to-one mapping. A unique… More >