P. Thilagavathi*, S. Karthikeyan
Intelligent Automation & Soft Computing, Vol.34, No.3, pp. 2035-2050, 2022, DOI:10.32604/iasc.2022.026651
Abstract Test data volume reduction and power consumption during testing time outlines are two main problems for Very Large Scale Integration (VLSI) gadgets. Most the code-based arrangements have been utilized to diminish test data volume, although the most notable way that test data volume is high. The switching action that happens between the test carriers leads would expand power consumption. This work presents a compression/decompression methodology for limiting the amount of test data that should be kept on a tester and conveyed to each center in a System on a Chip (SOC) during a test utilizing the Adaptive Multiscale Transformation Run… More >
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