Hojin Kang¹, Syed Asmat Ali Shah², HyungWon Kim^1,*

CMC-Computers, Materials & Continua, Vol.72, No.1, pp. 2127-2139, 2022, DOI:10.32604/cmc.2022.025798

Abstract This paper presents an energy efficient architecture for successive approximation register (SAR) analog to digital converter (ADC). SAR ADCs with a capacitor array structure have been widely used because of its simple architecture and relatively high speed. However, conventional SAR ADCs consume relatively high energy due to the large number of capacitors used in the capacitor array and their sizes scaled up along with the number of bits. The proposed architecture reduces the energy consumption as well as the capacitor size by employing a new array architecture that scales down the reference voltages instead of scaling up the capacitor sizes.… More >

V. Gowrishankar^1,*, K. Venkatachalam¹

CMC-Computers, Materials & Continua, Vol.60, No.3, pp. 947-957, 2019, DOI:10.32604/cmc.2019.07749

Abstract A high precision 10-bit successive approximation register analog to digital converter (ADC) designed and implemented in 32nm CNTFET process technology at the supply of 0.6V, with 73.24 dB SNDR at a sampling rate of 640 MS/s with the average power consumption of 120.2 μW for the Internet of things node. The key components in CNTFET SAR ADCs are binary scaled charge redistribution digital to analog converter using MOS capacitors, CNTFET based dynamic latch comparator and simple SAR digital code error correction logic. These techniques are used to increase the sampling rate and precision while ensuring the linearity, power consumption and… More >