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    ARTICLE

    Cache Memory Design for Single Bit Architecture with Different Sense Amplifiers

    Reeya Agrawal1,*, Anjan Kumar1, Salman A. AlQahtani2, Mashael Maashi3, Osamah Ibrahim Khalaf4, Theyazn H. H. Aldhyani5

    CMC-Computers, Materials & Continua, Vol.73, No.2, pp. 2313-2331, 2022, DOI:10.32604/cmc.2022.029019

    Abstract Most modern microprocessors have one or two levels of on-chip caches to make things run faster, but this is not always the case. Most of the time, these caches are made of static random access memory cells. They take up a lot of space on the chip and use a lot of electricity. A lot of the time, low power is more important than several aspects. This is true for phones and tablets. Cache memory design for single bit architecture consists of six transistors static random access memory cell, a circuit of write driver, and sense amplifiers (such as voltage… More >

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