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An Optimization Analysis of UBM Thicknesses and Solder Geometry on A Wafer Level Chip Scale Package Using Robust Methods

Heng-Cheng Lin1, Chieh Kung2, Rong-Sheng Chen1, Gin-Tiao Liang1

Department of Engineering Science, National Cheng Kung University, Tainan, Taiwan.
Department of Computer Application Engineering, Far East College, Tainan, Taiwan.

Computers, Materials & Continua 2006, 3(2), 55-64. https://doi.org/10.3970/cmc.2006.003.055

Abstract

Wafer level chip scale package (WLCSP) has been recognized providing clear advantages over traditional wire-bond package in relaxing the need of underfill while offering high density of I/O interconnects. Without the underfill, the solder joint reliability becomes more critical. Adding to the reliability concerns is the safety demand trend toward "green'' products on which unleaded material, e.g. lead-free solders, is required. The requirement of lead-free solders on the packages results in a higher reflow temperature profile in the package manufacturing process, in turn, complicating the reliability issue. This paper presents an optimization study, considering the fatigue reliability, for a wafer level chip scale IC package in which a Ti/Cu/Ni UBM is involved. A finite element model is developed for the package. The model employs Sn3.8Ag0.7Cu lead-free solders built on build-up layers with micro-vias. Finite element analyses are performed to study the mechanical behaviors of the package elements in which the solder as well as the UBM is of interest. Firstly, a Surface Evolver program is used to construct the solder based non-solder mask defined (NSMD) pad. Then, multi-purpose finite element software, ANSYStm, is used to create a double symmetric 3-D numerical model to investigate the mechanical behaviors including deformation, stress-strain relation as well as hysteresis loops for temperature cycles. The Garofalo-Arrhenius Creep Model is employed. A modified Coffin-Manson formula is also employed to estimate the fatigue life for the package. Finally, the Taguchi robust analysis is adopted for optimization analysis of UBM thicknesses and solder geometry. Our results show that thicker UBM layers tend to increase the fatigue life while a small solder pad will prolong the fatigue life and as volume increases so does the fatigue life. From the results of Taguchi robust analysis, it is shown that among the factors of UBM layer thickness, solder pad radius and solder volume, the solder volume is the most dominating factor on the fatigue life of the package. The optimal combination of UBM thickness set at 0.0066 mm (level 3), solder pad radius set at 0.10 mm (Level 1), and solder volume set at 0.020 mm3 (Level 3) contributes the greatest fatigue life of 1229 cycles which is 448% gained over our reference package model.

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APA Style
Lin, H., Kung, C., Chen, R., Liang, G. (2006). An optimization analysis of UBM thicknesses and solder geometry on A wafer level chip scale package using robust methods. Computers, Materials & Continua, 3(2), 55-64. https://doi.org/10.3970/cmc.2006.003.055
Vancouver Style
Lin H, Kung C, Chen R, Liang G. An optimization analysis of UBM thicknesses and solder geometry on A wafer level chip scale package using robust methods. Comput Mater Contin. 2006;3(2):55-64 https://doi.org/10.3970/cmc.2006.003.055
IEEE Style
H. Lin, C. Kung, R. Chen, and G. Liang, “An Optimization Analysis of UBM Thicknesses and Solder Geometry on A Wafer Level Chip Scale Package Using Robust Methods,” Comput. Mater. Contin., vol. 3, no. 2, pp. 55-64, 2006. https://doi.org/10.3970/cmc.2006.003.055



cc Copyright © 2006 The Author(s). Published by Tech Science Press.
This work is licensed under a Creative Commons Attribution 4.0 International License , which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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