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Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder

B. Annapoorani*, P. Marikkannu

Anna University Regional Campus, Coimbatore, Tamilnadu, India

* Corresponding Author: B. Annapoorani. Email: email

Computer Systems Science and Engineering 2023, 45(3), 2659-2672.


The adders are the vital arithmetic operation for any arithmetic operations like multiplication, subtraction, and division. Binary number additions are performed by the digital circuit known as the adder. In VLSI (Very Large Scale Integration), the full adder is a basic component as it plays a major role in designing the integrated circuits applications. To minimize the power, various adder designs are implemented and each implemented designs undergo defined drawbacks. The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more. To overcome such issues and to obtain better performance, a novel parallel adder is proposed. The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability. This proposed novel parallel adder is attained from the carry look-ahead adder. The merits of this suggested adder are better speed, power consumption and delay, and the capability in driving. Thus designed adders are verified for different supply, delay, power, leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder (MCCA), Carry Look Ahead Adder (CLAA), Carry Select Adder (CSLA), Carry Select Adder (CSA) and other adders.


Cite This Article

APA Style
Annapoorani, B., Marikkannu, P. (2023). Performance measurement of energy efficient and highly scalable hybrid adder. Computer Systems Science and Engineering, 45(3), 2659-2672.
Vancouver Style
Annapoorani B, Marikkannu P. Performance measurement of energy efficient and highly scalable hybrid adder. Comput Syst Sci Eng. 2023;45(3):2659-2672
IEEE Style
B. Annapoorani and P. Marikkannu, "Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder," Comput. Syst. Sci. Eng., vol. 45, no. 3, pp. 2659-2672. 2023.

cc This work is licensed under a Creative Commons Attribution 4.0 International License , which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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