Mohanapriya Marimuthu¹, Santhosh Rajendran², Reshma Radhakrishnan², Kalpana Rengarajan³, Shahzada Khurram⁴, Shafiq Ahmad⁵, Abdelaty Edrees Sayed⁵, Muhammad Shafiq^6,*

CMC-Computers, Materials & Continua, Vol.74, No.3, pp. 4729-4745, 2023, DOI:10.32604/cmc.2023.033020

Abstract Continuous improvements in very-large-scale integration (VLSI) technology and design software have significantly broadened the scope of digital signal processing (DSP) applications. The use of application-specific integrated circuits (ASICs) and programmable digital signal processors for many DSP applications have changed, even though new system implementations based on reconfigurable computing are becoming more complex. Adaptable platforms that combine hardware and software programmability efficiency are rapidly maturing with discrete wavelet transformation (DWT) and sophisticated computerized design techniques, which are much needed in today’s modern world. New research and commercial efforts to sustain power optimization, cost savings, and improved runtime effectiveness have been initiated… More >

B. Annapoorani^*, P. Marikkannu

Computer Systems Science and Engineering, Vol.45, No.3, pp. 2659-2672, 2023, DOI:10.32604/csse.2023.025075

Abstract The adders are the vital arithmetic operation for any arithmetic operations like multiplication, subtraction, and division. Binary number additions are performed by the digital circuit known as the adder. In VLSI (Very Large Scale Integration), the full adder is a basic component as it plays a major role in designing the integrated circuits applications. To minimize the power, various adder designs are implemented and each implemented designs undergo defined drawbacks. The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more. To overcome such issues and to obtain better… More >

E. Poovannan^*, S. Karthik

CMC-Computers, Materials & Continua, Vol.74, No.1, pp. 2161-2177, 2023, DOI:10.32604/cmc.2023.032512

Abstract The difference between circuit design stage and time requirements has broadened with the increasing complexity of the circuit. A big database is needed to undertake important analytical work like statistical method, heat research, and IR-drop research that results in extended running times. This unit focuses on the assessment of test strength. Because of the enormous number of successful designs for current models and the unnecessary time required for every test, maximum energy ratings with all tests cannot be achieved. Nevertheless, test safety is important for producing trustworthy findings to avoid loss of output and harm to the chip. Generally, effective… More >

M. Sundar Prakash Balaji^1,*, V. R. Vijaykumar², Kamalraj Subramaniam³, M. Kannan⁴, V. Ayyem Pillai⁵

Intelligent Automation & Soft Computing, Vol.35, No.3, pp. 3155-3168, 2023, DOI:10.32604/iasc.2023.028969

Abstract The current research work proposed a novel optimization-based 2D-SIMM (Two-Dimensional Sine Iterative chaotic map with infinite collapse Modulation Map) model for image encryption. The proposed 2D-SIMM model is derived out of sine map and Iterative Chaotic Map with Infinite Collapse (ICMIC). In this technique, scrambling effect is achieved with the help of Chaotic Shift Transform (CST). Chaotic Shift Transform is used to change the value of pixels in the input image while the substituted value is cyclically shifted according to the chaotic sequence generated by 2D-SIMM model. These chaotic sequences, generated using 2D-SIMM model, are sensitive to initial conditions. In… More >

L. Vasanth^*, N. J. R. Muniraj

Intelligent Automation & Soft Computing, Vol.33, No.2, pp. 955-966, 2022, DOI:10.32604/iasc.2022.022979

Abstract Multiple Input Multiple Output (MIMO) is an advanced communication technology that is often used for secure data transfer for military and other applications while transmitting data with high error and noise. To address this issue, a step-by-step hybrid Quadrature Phase Shift Keying (QPSK) modulation scheme in the MIMO system for a complex Very Large-Scale Integration (VLSI) format is recommended. When compared to Binary Phase Shift Keying (BPSK), this approach provides twice the data rate while using half the bandwidth. The complexity is lowered through multiplication and addition, as well as error and noise reduction in data transport, and MIMO detection… More >

P. PattunnaRajam^{1, *}, Reeba korah², G. Maria Kalavathy³

CMC-Computers, Materials & Continua, Vol.54, No.3, pp. 251-268, 2018, DOI:10.3970/cmc.2018.054.251

Abstract This paper presents an automated POCOFAN-POFRAME algorithm that partitions large combinational digital VLSI circuits for pseudo exhaustive testing. In this paper, a simulation framework and partitioning technique are presented to guide VLSI circuits to work under with fewer test vectors in order to reduce testing time and to develop VLSI circuit designs. This framework utilizes two methods of partitioning Primary Output Cone Fanout Partitioning (POCOFAN) and POFRAME partitioning to determine number of test vectors in the circuit. The key role of partitioning is to identify reconvergent fanout branch pairs and the optimal value of primary input node N and fanout… More >