Open Access

ARTICLE

High Efficient Reconfigurable and Self Testable Architecture for Sensor Node

G. Venkatesan^1,*, N. Ramadass²

1 Department of Electronics and Instrumentation Engineering, Meenakshi College of Engineering, Chennai, India
2 Department of Electronics and Communication Engineering, CEG Campus, Anna University, Chennai, India

* Corresponding Author: G. Venkatesan. Email:

Computer Systems Science and Engineering 2023, 46(3), 3979-3991. https://doi.org/10.32604/csse.2023.031627

Received 22 April 2022; Accepted 27 June 2022; Issue published 03 April 2023

Abstract

Sensor networks are regularly sent to monitor certain physical properties that run in length from divisions of a second to many months or indeed several years. Nodes must advance their energy use for expanding network lifetime. The fault detection of the network node is very significant for guaranteeing the correctness of monitoring results. Due to different network resource constraints and malicious attacks, security assurance in wireless sensor networks has been a difficult task. The implementation of these features requires larger space due to distributed module. This research work proposes new sensor node architecture integrated with a self-testing core and cryptoprocessor to provide fault-free operation and secured data transmission. The proposed node architecture was designed using Verilog programming and implemented using the Xilinx ISE tool in the Spartan 3E environment. The proposed system supports the real-time application in the range of 33 nanoseconds. The obtained results have been compared with the existing Microcontroller-based system. The power consumption of the proposed system consumes only 3.9 mW, and it is only 24% percentage of AT mega-based node architecture.

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Keywords

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