High Efficient Reconfigurable and Self Testable Architecture for Sensor Node
Department of Electronics and Instrumentation Engineering, Meenakshi College of Engineering, Chennai, India
2 Department of Electronics and Communication Engineering, CEG Campus, Anna University, Chennai, India
* Corresponding Author: G. Venkatesan. Email:
Computer Systems Science and Engineering 2023, 46(3), 3979-3991. https://doi.org/10.32604/csse.2023.031627
Received 22 April 2022; Accepted 27 June 2022; Issue published 03 April 2023
AbstractSensor networks are regularly sent to monitor certain physical properties that run in length from divisions of a second to many months or indeed several years. Nodes must advance their energy use for expanding network lifetime. The fault detection of the network node is very significant for guaranteeing the correctness of monitoring results. Due to different network resource constraints and malicious attacks, security assurance in wireless sensor networks has been a difficult task. The implementation of these features requires larger space due to distributed module. This research work proposes new sensor node architecture integrated with a self-testing core and cryptoprocessor to provide fault-free operation and secured data transmission. The proposed node architecture was designed using Verilog programming and implemented using the Xilinx ISE tool in the Spartan 3E environment. The proposed system supports the real-time application in the range of 33 nanoseconds. The obtained results have been compared with the existing Microcontroller-based system. The power consumption of the proposed system consumes only 3.9 mW, and it is only 24% percentage of AT mega-based node architecture.
Like numerous key advancements, Wireless Sensor Networks (WSN) began from military applications, for example, the systems of acoustic sensors previously conveyed during the 1950 s for submarines . In the 1980 s, the United States defense advanced research projects agency concentrated its exploration on computation, distributed sensing, and communication within the Distributed Sensor Networks (DSN) . In the 1990 s, the advancements in wireless communication technologies enabled actual WSNs from wired DSNs [3,4]. This opened the WSN innovation to a wide range of nonmilitary personnel applications, for example, checking ecological boundaries and modern procedures, the following objects, and identifying events .
These days, the exploration endeavors on WSNs are converged with embedded frameworks and the arrangement of framework planning techniques, yielding Cyber Physical Systems (CPS) . Many Internet of Things (IoT) solutions are provided in WSNs [7,8]. CPS is focused on serving a variety of applications, and is not restricted to specific nodes. CPS nodes get connected to open communication networks, thus causing significant development of the IoT . For a few applications like home automation and smart home appliances, which require less data rate, IEEE [802.15.4]-based protocol suffices. Often, WSNs are small tiny units connected with several sensor nodes with a specific network topology. Intermediate nodes also contribute to the data transmission from one end to the other  with applications in critical areas like monitoring environmental threats and disaster management . It is essential to secure the nodes as they may be damaged by harsh weather conditions which may sometimes cause the whole system to fail. Along these lines, the fault detection of the node network is significant for guaranteeing the exactness of checking results.
A robust security protocol for communicating through WSN is mandatory if it has to be used in some mission-critical tasks. However, providing satisfactory security protection in WSNs has been challenging due to various network and resource constraints and malicious attacks. Hence specific Integrated circuits, Application Specific Integrated Circuits (ASIC) can work efficiently managing data security and accelerate computation and data transfer [11,12]. Because of their absence of adaptability and high Non Recurring Engineering (NRE) costs, ASIC is not a feasible choice for the research model and is subsequently not looked into in more detail. Programmable integrated circuits such as a Field Programmable Gate Array (FPGA) would be a good choice considering the massively parallel hardware available and low NRE cost compared to ASIC. Hence our research work proposes wireless sensor node architecture integrated with a self-testing core and cryptoprocessor to provide fault-free operation along with secured data transmission. To solve the power consumption and increase the speed of the operation, this research work proposes the sensor node architecture, which is designed in FPGA with reconfigurable selection.
This paper is organized in such a way that Section 1 gives the introduction to the node architecture. Related works are discussed in Section 3. The proposed secured and self-testable wireless sensor node architecture has been explained in this Section 4. Results of the proposed research work have been discussed and analyzed in Section 5. The conclusion of the proposed sensor node architecture has been explained in this Section 6.
A sensor network comprises various little embedded designs (named sensor nodes), which convey remotely to resolve a joint task. They are commonly utilized as effectively deployable information acquisition systems to screen the transient and spatial qualities of surrounding physical quantities, for example, Temperature, Pressure, Flow, Humidity, Structural vibration, etc. Fig. 1 shows the sample monitoring application of WSN in the dedicated gateway node all the information accumulated by the WSN has to be collected.
The collected information in the gateway is stored steadily or sent to a remote base station through a wide area network such as a mobile cellular radio link. Along with the signal monitoring, the Nodes are used to track the objects or the signal collecting nodes may be attached to a WSN application . Likewise, the necessities and capacities of the nodes shift emphatically between various applications, and even inside a specific network, the architecture of ordinary WSN nodes comprises the five conventional units shown in Fig. 2. Digital or analog sensors catch the pertinent signals at fixed intervals ranging from a few seconds in ecological monitoring  down to a few milliseconds in vibration-based secondary health checking  or even beneath in acoustic restriction applications . Before processing or transmission sampled data should be stored in the memory module.
Normally the internal memory of any processor is limited to a few kilobytes. This internal memory is not enough to store long-duration sampled data. So, Flash Programmable Random Access Memory (FRAM) or Flash memory should be attached with the WSN nodes [16–18]. The main part of the node is a processor that controls or coordinates the memory, transceiver, and sensors. Most of the simple nodes are designed based on Atmel or the 16 bit Texas Instrument controller. More sophisticated nodes are designed using the advanced reduced instruction set computer machine microcontrollers or power full digital signal processors .
Apart from the regular processor, the integration of ASICs of proposed by some of the WSN projects [20,21]. Security is essential for the application, for example, battlefield, environmental observation, and smart home to be executed. To ensure the data security of WSN, it is important to recognize nodes [21–22]. In any case, it is a test for the nodes to run encryption calculations and store information because of the restricted computational capacity and resources. Compare to the Rivest–Shamir–Adleman (RSA), Advanced Encryption Standards (AES) takes lesser time and gives better security than Secure Hash Algorithms (SHA) . To reduce the power consumption altering the data path is suggested several multipliers reduced in . To prove the hardware efficiency the architecture can be implemented in a field-programmable gate array . In , a novel FPGA implementation of a new AES architecture is analyzed and compared with the different AES implementations and proved that the new architecture has high speed and reduced area. To guarantee a long-term activity without the power supply in an environment, a nonconventional power supply gracefully has been chosen and a low power utilization structure of a water level observing station was proposed in . A low-power WSN for smart grid application along with cyber security is presented in  can sense and separate various attacks in a well-organized manner.
The proposed wireless sensor node architecture performs three major functions such as self testable, automatic or manual transmission, secured or unsecured transmission. All three functions have been implemented by three major hardware units.
1. Testing core responsible for testing the node whenever initializing the node.
2. A regular processor is used to perform the computation and transmission with manual and automatic modes.
3. A cryptoprocessor for transmitting the collected data a secured manner.
High-speed low area AES architecture has been proposed for secured transmission. All three operations are controlled by a state machine which depends on the inputs from sensor node architecture. Fig. 3 shows the proposed sensor node architecture. The input pins are automatic/manual, secured or unsecured, clock, reset, data input from Analog to Digital Converter (ADC). The output pins are data out which enable and ensure the transmitted data is collected from one of the sensors from the group of eight sensors. Tx completed pin indicates the completion of Transmission. Three-bit ADC selection pin selects the ADC input to convert the analog to digital data from any one of the inputs. An output pin ADC pin enables the ADC for the conversion. The detailed block diagram of the proposed node architecture is given in Fig. 4.
The main function of node architecture is collecting the data from various sensors through the ADC unit and computing the required format. The computed data is encrypted using a crypto processor and includes the error-correcting codes before transmitting. The entire control signal required for the remaining units is issued by the data process unit only. So the major part of the work of wireless sensor node architecture is carried out by the data processor unit only. The major unit of data process is sensor subsystem, controlling of ADC unit and process of collecting data. The function of the data process unit is explained through the state machine and flow charts given in the following sections.
Data process unit comprises the physical sensors and ADC. It acts as the interface between the physical environment and virtual world, i.e., collecting data from the environment and converting this data from analog to digital signal for smooth processing.
a. Sensor: A sensor senses physical parameters such as temperature, flow, pressure, level, motion, speed, etc, and convert them into electrical (analog) signal. A WSN incorporates countless sensor nodes with every node containing at least one sensor relying upon the application territory. There is a range of sensor types that can be employed in WSNs. An example of sensor classification is active and passive sensors. Active sensors do not need any external power supply for conversion of physical quantity into electrical quantity examples for active transducers/sensors are thermocouple and piezoelectric transducer. Alternatively, passive sensors require an external power supply to convert physical quantity into electrical quantity. Resistance thermometers, linear variable differential transformer, strain gauges are good examples of passive sensors.
b. Analog-to-Digital Converter (ADC): The output of a sensor is an analog signal. This means there needs to be an interface between the sensor and the digital processor (microcontroller). The ADC converts the output of a sensor which is a continuous, analog signal into a digital signal .
Fig. 5 shows the state machine of the proposed sensor node architecture.
During testing mode, the processor selects one channel out of 8 input channels. And the ADC is connected first with a maximum reference voltage and the converted digital signal is verified with register. Second, the input is connected with 50% of a reference voltage and the converted digital equivalent is compared with stored value if it is within the tolerance it goes to test the next input value otherwise sets the bit as a fault, and information is passed as the specific channel failed. If the 50% conversion voltage is correct then the next input to the channel is ground and compare the converted result with the tolerance level for setting the channel is a defect or not. Similarly, all the channels are tested for three cases and then the fault field in the packet is set as a logical one. After satisfying the operation of the ADC the self-test verifies the cryptoprocessor if the architecture is selected as secured otherwise the processor continues the regular operation. The cryptoprocessor is tested by sending a predefined input and verifying the output with stored results if the output of the cryptoprocessor is the same as the stored results then the fault field in the packet is cleared otherwise it is set as a logical one. The processing is explained in Fig. 6. The tolerance is set as the given equation
where Ya is the stored result and Yb is the output of cryptoprocessor
The AES can be customized in programming or worked with unadulterated equipment. Anyway, FPGAs offer a snappier, more adaptable arrangement. This research proposes a crypto processor using the AES algorithm concerning FPGA and the Verilog. In this research, a high-performance AES architecture implementation with MUX-based substitution box (S-Box) and random round selection is proposed. The byte substitution process implemented by S-Box is a significant part of the AES. In the novel FPGA implementation, a new AES architecture has been analyzed and compared in terms of area, speed and power with the different AES implementations. This crypto processor consists of 20-pins as well as works with 3.3 V power supply. This processor can be work at a 100 MHz of maximum frequency.
The 10-byte packet format for the self-testable unit is arranged in little-endian mode. The byte 0, 1, 2, 3 5, 6, 7, 8 are assigned to ADC output channel 0 to 7 respectively. The ADC accept maximum of eight channels. The 4th byte is reserved for user operation. The 9th byte contains the control and status bits. The 7th bit of 9th byte is used for testing result up dation. The bit is set as the node fails during the testing operation otherwise fault free. The 6th bit indicates that the sensor value is normal or abnormal. This bit is set when any channel output is abnormal. The 5th bit is used to indicate the processor is in secured or unsecured mode. Fig. 7 shows the Packet format used in the proposed node architecture.
To improve the reliability of remote transmission, an Error Correction Code (ECC) was included in the proposed testable WSN. After the EEC scrambled the signs, the ECC includes extra bits called redundancy codes before the transmission of information. The beneficiary can check whether transmission information is right or with blunder before decoding the information received. By creating a polynomial function, the ECC procedure can diminish transmission blunder.
All the three modules in the proposed architecture have been designed and implemented using Verilog programming. These three basic units are controlled by state machines and it has also been designed using Verilog programming. Individual units are simulated with the help of the ModelSim SE 6.5b version simulator. The mealy model is used to design the state machine. There are 12 states in the design to control the operation of node architecture. The entire architecture has been synthesized using the Xilinx EDA tool for hardware implementation. Table 1 shows the device utilization summary and power consumption of the proposed sensor node architecture for the target of Spartan 3E FPGA. Fig. 8 shows the simulation result of node architecture.
From Table 1 the data process unit consumes 7347 slices out of 14176 slices consumed by the overall units. Except the Crypto processor the proposed featured processor increases 6829 slices. At the cost of area increased, the proposed system offers addition features such as self testing, error correction and Crypto processing. This has been a major area of overall node architecture. Fig. 9 shows the device utilization summary of node architecture. From Fig. 9, the area is utilized by the various units such as testing unit, cryptoprocessor, Data processor, ECC unit, and control units.
The percentage of area occupied by the various units is shown in Fig. 10. From the Fig. 10, the data process unit consumes 52%. The remaining units such as testing and cryptoprocessor are the additional units apart from the basic unit and also these units consume only less area compared with the data process unit. It is 12% and 23% respectively. From the Look Up Table (LUT) utilization chart, the data process unit consumes 47% and the testing, crypto processors consume 14% and 24% respectively.
Fig. 11 shows the propagation delay of different units of the proposed node architecture. The data process unit of node architecture is the major essential unit of node architecture and also it takes a longer propagation delay of overall node architecture. Its takes 23.7 ns, the frequency (T) of operation of this data process unit is 42.19 MHz. Next to the data process, the cryptoprocessor takes a propagation delay of 0.55 ns. The remaining units will be operated with a higher frequency than the data process and cryptoprocessor.
Fig. 12 shows the power consumed by the various units of the proposed node architecture. Out of all units, the data processor unit consumes 1.939 mW. This power consumption is 51 percent of the power consumption of overall units of node architecture. The major operation of node architecture is handled by the data processor, It controls the ADC operation as well as collecting the data from all sensors and converting them to ciphertext if the security is included. Otherwise, the collected data is added with ECC and converted to packet format before transmission. To test the node architecture the proposed testing unit takes 4.3 nanoseconds.
Fig. 13 shows the Power Delay Product (PDP) of node architecture in terms of various parts power delay product. From the chart, the ECC unit power delay product is very negligible compared with the data process unit. Even though the ECC unit consumes a considerable area, the power delay product is very less. The area consumed by the cryptoprocessor is 24% but the power delay product is only 8.36 pJ. It is only 18% of the data process unit.
Table 2 shows the comparison of power consumed by the proposed method and various microprocessor implementations. From Table 2, it is clear that the proposed work consumes only 3.9 mW compared with the 8051 microcontroller-based node architecture consumes 53.6 mW  and ATmega 2560 based architecture consumes 15 mW power .
Sensor Network is a significant segment of present-day mobile communication systems. However, node execution is genuinely influenced because of the process unit failures. Therefore, a low-power consumption fault detection method in WSNs has been proposed in this work. The testing mechanism consumes only 2.7% of the data process unit. Similarly, next to the data process unit, the crypto process consumes 50% of the area of the data process unit. The power delay product of this unit is 18% of the data process unit. All other units of the proposed node architecture consume only 25% PDP of main processing. The power consumption of the proposed WSN architecture is 24% of the wireless sensor node architecture implemented by Dhuna using an Atmega processor. The frequency of operation of the proposed system is 29.94 MHz and the system supports the real-time application in the range of 33 nanoseconds. The advantage of the proposed sensor network architecture is programmable with security and testing units.
Funding Statement: The authors received no specific funding for this study.
Conflicts of Interest: The authors declare that they have no conflicts of interest to report regarding the present study.
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