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  • Open Access

    ARTICLE

    FPGA Optimized Accelerator of DCNN with Fast Data Readout and Multiplier Sharing Strategy

    Tuo Ma, Zhiwei Li, Qingjiang Li*, Haijun Liu, Zhongjin Zhao, Yinan Wang

    CMC-Computers, Materials & Continua, Vol.77, No.3, pp. 3237-3263, 2023, DOI:10.32604/cmc.2023.045948

    Abstract With the continuous development of deep learning, Deep Convolutional Neural Network (DCNN) has attracted wide attention in the industry due to its high accuracy in image classification. Compared with other DCNN hardware deployment platforms, Field Programmable Gate Array (FPGA) has the advantages of being programmable, low power consumption, parallelism, and low cost. However, the enormous amount of calculation of DCNN and the limited logic capacity of FPGA restrict the energy efficiency of the DCNN accelerator. The traditional sequential sliding window method can improve the throughput of the DCNN accelerator by data multiplexing, but this method’s data multiplexing rate is low… More >

  • Open Access

    ARTICLE

    A XFEM LAGRANGE MULTIPLIER TECHNIQUE FOR STEFAN PROBLEMS

    Dave Martina,b,† , Hicham Chaoukia,b, Jean-Loup Roberta, Donald Zieglerc, Mario Fafarda,b

    Frontiers in Heat and Mass Transfer, Vol.7, pp. 1-9, 2016, DOI:10.5098/hmt.7.31

    Abstract The two dimensional phase change problem was solved using the extended finite element method with a Lagrange formulation to apply the interface boundary condition. The Lagrange multiplier space is identical to the solution space and does not require stabilization. The solid-liquid interface velocity is determined by the jump in heat flux across the i nterface. Two methods to calculate the jump are used and c ompared. The first is based on an averaged temperature gradient near the interface. The second uses the Lagrange multiplier values to evaluate the jump. The Lagrange multiplier based approach was shown to be more robust… More >

  • Open Access

    ARTICLE

    MODELLING OF PHASE CHANGE WITH NON-CONSTANT DENSITY USING XFEM AND A LAGRANGE MULTIPLIER

    Dave Martina,b,† , Hicham Chaoukia,b, Jean-Loup Roberta, Donald Zieglerc, Mario Fafarda,b

    Frontiers in Heat and Mass Transfer, Vol.7, pp. 1-11, 2016, DOI:10.5098/hmt.7.40

    Abstract A two phase model for two-dimensional solidification problems with variable densities was developed by coupling the Stefan problem with the Stokes problem and applying a mass conserving velocity condition on the phase change interface. The extended finite element method (XFEM) was used to capture the strong discontinuity of the velocity and pressure as well as the jump in heat flux at the i nterface. The melting temperature and velocity condition were imposed on the interface using a Lagrange multiplier and the penalization method, respectively. The resulting formulations were then coupled using a fixed point iteration a lgorithm. Three examples were… More >

  • Open Access

    ARTICLE

    Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra

    Marwa A. Elmenyawi1,2,*, Radwa M. Tawfeek1

    Computer Systems Science and Engineering, Vol.46, No.2, pp. 1827-1844, 2023, DOI:10.32604/csse.2023.036474

    Abstract One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design is mandatory for efficient computing systems. In designing low-energy dissipation circuits, reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity. This paper introduces an efficient signed/unsigned 4 × 4 reversible Vedic multiplier with minimum quantum cost. The Vedic multiplier is considered fast as it generates all partial product and their sum in one step. This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output. First, the unsigned Vedic multiplier is designed based on… More >

  • Open Access

    ARTICLE

    Truncation and Rounding-Based Scalable Approximate Multiplier Design for Computer Imaging Applications

    S. Rooban1,*, A. Yamini Naga Ratnam1, M. V. S. Ramprasad2, N. Subbulakshmi3, R. Uma Mageswari4

    CMC-Computers, Materials & Continua, Vol.73, No.3, pp. 5169-5184, 2022, DOI:10.32604/cmc.2022.027974

    Abstract Advanced technology used for arithmetic computing application, comprises greater number of approximate multipliers and approximate adders. Truncation and Rounding-based Scalable Approximate Multiplier (TRSAM) distinguish a variety of modes based on height (h) and truncation (t) as TRSAM (h, t) in the architecture. This TRSAM operation produces higher absolute error in Least Significant Bit (LSB) data shift unit. A new scalable approximate multiplier approach that uses truncation and rounding TRSAM (3, 7) is proposed to increase the multiplier accuracy. With the help of foremost one bit architecture, the proposed scalable approximate multiplier approach reduces the partial products. The proposed approximate TRSAM… More >

  • Open Access

    ARTICLE

    An Optimized Deep-Learning-Based Low Power Approximate Multiplier Design

    M. Usharani1,*, B. Sakthivel2, S. Gayathri Priya3, T. Nagalakshmi4, J. Shirisha5

    Computer Systems Science and Engineering, Vol.44, No.2, pp. 1647-1657, 2023, DOI:10.32604/csse.2023.027744

    Abstract Approximate computing is a popular field for low power consumption that is used in several applications like image processing, video processing, multimedia and data mining. This Approximate computing is majorly performed with an arithmetic circuit particular with a multiplier. The multiplier is the most essential element used for approximate computing where the power consumption is majorly based on its performance. There are several researchers are worked on the approximate multiplier for power reduction for a few decades, but the design of low power approximate multiplier is not so easy. This seems a bigger challenge for digital industries to design an… More >

  • Open Access

    ARTICLE

    Optimized Image Multiplication with Approximate Counter Based Compressor

    M. Maria Dominic Savio1,*, T. Deepa1, N. Bharathiraja2, Anudeep Bonasu3

    CMC-Computers, Materials & Continua, Vol.72, No.2, pp. 3815-3834, 2022, DOI:10.32604/cmc.2022.025924

    Abstract The processor is greatly hampered by the large dataset of picture or multimedia data. The logic of approximation hardware is moving in the direction of multimedia processing with a given amount of acceptable mistake. This study proposes various higher-order approximate counter-based compressor (CBC) using input shuffled 6:3 CBC. In the Wallace multiplier using a CBC is a significant factor in partial product reduction. So the design of 10-4, 11-4, 12-4, 13-4 and 14-4 CBC are proposed in this paper using an input shuffled 6:3 compressor to attain two stage multiplications. The input shuffling aims to reduce the output combination of… More >

  • Open Access

    ARTICLE

    Design of Precise Multiplier Using Inexact Compressor for Digital Signal Processing

    Nagarajan Shanmugam*, Vijeyakumar Krishnasamy Natarajan, Kalaiselvi Sundaram, Saravanakumar Natarajan

    Computer Systems Science and Engineering, Vol.42, No.2, pp. 619-638, 2022, DOI:10.32604/csse.2022.021008

    Abstract In the recent years, error recovery circuits in optimized data path units are adopted with approximate computing methodology. In this paper the novel multipliers have effective utilization in the newly proposed two different 4:2 approximate compressors that generate Error free Sum (ES) and Error free Carry (EC). Proposed ES and Proposed EC in 4:2 compressors are used for performing Partial Product (PP) compression. The structural arrangement utilizes Dadda structure based PP. Due to the regularity of PP arrangement Dadda multiplier is chosen for compressor implementation that favors easy standard cell ASIC design. In this, the proposed compression idealogy are more… More >

  • Open Access

    ARTICLE

    Reversible Logic Based MOS Current Mode Logic Implementation in Digital Circuits

    S. Sharmila Devi1,*, V. Bhanumathi2

    CMC-Computers, Materials & Continua, Vol.70, No.2, pp. 3609-3624, 2022, DOI:10.32604/cmc.2022.020426

    Abstract Now a days, MOS Current Mode Logic (MCML) has emerged as a better alternative to Complementary Metal Oxide Semiconductor (CMOS) logic in digital circuits. Recent works have only traditional logic gates that have issues with information loss. Reversible logic is incorporated with MOS Current Mode Logic (MCML) in this proposed work to solve this problem, which is used for multiplier design, D Flip-Flop (DFF) and register. The minimization of power and area is the main aim of the work. In reversible logic, the count of outputs and inputs is retained as the same value for creating one-to-one mapping. A unique… More >

  • Open Access

    ARTICLE

    Optimal Control and Spectral Collocation Method for Solving Smoking Models

    Amr M. S. Mahdy1,*, Mohamed S. Mohamed1, Ahoud Y. Al Amiri2, Khaled A. Gepreel1

    Intelligent Automation & Soft Computing, Vol.31, No.2, pp. 899-915, 2022, DOI:10.32604/iasc.2022.017801

    Abstract In this manuscript, we solve the ordinary model of nonlinear smoking mathematically by using the second kind of shifted Chebyshev polynomials. The stability of the equilibrium point is calculated. The schematic of the model illustrates our proposition. We discuss the optimal control of this model, and formularize the optimal control smoking work through the necessary optimality cases. A numerical technique for the simulation of the control problem is adopted. Moreover, a numerical method is presented, and its stability analysis discussed. Numerical simulation then demonstrates our idea. Optimal control for the model is further discussed by clarifying the optimal control through… More >

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