Sheng Xiao1,2,*, Jing He3, Xi Yang4, Heng Zhou1, Yujie Yuan1
Computer Systems Science and Engineering, Vol.40, No.1, pp. 273-286, 2022, DOI:10.32604/csse.2022.019106
Abstract Timing speculative (TS) architecture is promising for improving the energy efficiency of microprocessors. Error recovery units, designed for tolerating occasional timing errors, have been used to support a wider range of voltage scaling, therefore to achieve a better energy efficiency. More specifically, the timing error rate, influenced mainly by data forwarding, is the bottleneck for voltage down-scaling in TS processors. In this paper, a new Timing Error Aware Register Allocation method is proposed. First, we designed the Dependency aware Interference Graph (DIG) construction to get the information of Read after Write (RAW) in programs. To build the construction, we get… More >
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