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Timing Error Aware Register Allocation in TS

Sheng Xiao1,2,*, Jing He3, Xi Yang4, Heng Zhou1, Yujie Yuan1

1 Information Science and Engineering Department, Hunan First Normal University, Changsha, 410205, China
2 Computer School, Wuhan University, Wuhan, 430072, China
3 Department of Computer Science, Kennesaw State University, Kennesaw, 30144-5588, USA
4 Hunan Guangyi Experimental Middle School, Changsha, 410205, China

* Corresponding Author: Sheng Xiao. Email: email

Computer Systems Science and Engineering 2022, 40(1), 273-286. https://doi.org/10.32604/csse.2022.019106

Abstract

Timing speculative (TS) architecture is promising for improving the energy efficiency of microprocessors. Error recovery units, designed for tolerating occasional timing errors, have been used to support a wider range of voltage scaling, therefore to achieve a better energy efficiency. More specifically, the timing error rate, influenced mainly by data forwarding, is the bottleneck for voltage down-scaling in TS processors. In this paper, a new Timing Error Aware Register Allocation method is proposed. First, we designed the Dependency aware Interference Graph (DIG) construction to get the information of Read after Write (RAW) in programs. To build the construction, we get the disassemble code as input and suppose that there are unlimited registers, the same way as so-called virtual registers in many compilers. Then we change the disassemble codes to the SSA form for each basic block to make sure the registers are defined only once. Based on the DIG construction, registers were reallocated to eliminate the timing error, by loosening the RAW dependencies. We construct the DIG for each function of the program and sort the edge of DIG by an increasing weight order. Since a smaller weighted-edge value means that its owner nodes have more frequent access in instruction flows, we expect it in different registers with no read-write dependency. At the same time, we make sure that there are no additional new spill codes emerging in our algorithm to minimize the rate of spill code. A high rate of spill code will not only decrease the performance of the system but also increase the unexpected read-write dependency. Next, we reallocate the registers by weight order in turn to loosen the RAW dependencies. Furthermore, we use the NOP operation to pad the instructions with a minimal distance value of 2. Experiment results showed that the average distance of RAW dependencies was increased by over 20%.

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Cite This Article

APA Style
Xiao, S., He, J., Yang, X., Zhou, H., Yuan, Y. (2022). Timing error aware register allocation in TS. Computer Systems Science and Engineering, 40(1), 273-286. https://doi.org/10.32604/csse.2022.019106
Vancouver Style
Xiao S, He J, Yang X, Zhou H, Yuan Y. Timing error aware register allocation in TS. Comput Syst Sci Eng. 2022;40(1):273-286 https://doi.org/10.32604/csse.2022.019106
IEEE Style
S. Xiao, J. He, X. Yang, H. Zhou, and Y. Yuan "Timing Error Aware Register Allocation in TS," Comput. Syst. Sci. Eng., vol. 40, no. 1, pp. 273-286. 2022. https://doi.org/10.32604/csse.2022.019106



cc This work is licensed under a Creative Commons Attribution 4.0 International License , which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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