Sheng Xiao^1,*, Yong Chen², Jing He³, Xi Yang⁴

Computer Systems Science and Engineering, Vol.46, No.3, pp. 3527-3540, 2023, DOI:10.32604/csse.2023.027081

Abstract Read-write dependency is an important factor restricting software efficiency. Timing Speculative (TS) is a processing architecture aiming to improve energy efficiency of microprocessors. Timing error rate, influenced by the read-write dependency, bottlenecks the voltage down-scaling and so the energy efficiency of TS processors. We proposed a method called Read-Write Dependency Aware Register Allocation. It is based on the Read-Write Dependency aware Interference Graph (RWDIG) conception. Registers are reallocated to loosen the read-write dependencies, so resulting in a reduction of timing errors. The traditional no operation (Nop) padding method is also redesigned to increase the distance value to above 2. We… More >

Sheng Xiao^1,2,*, Jing He³, Xi Yang⁴, Heng Zhou¹, Yujie Yuan¹

Computer Systems Science and Engineering, Vol.40, No.1, pp. 273-286, 2022, DOI:10.32604/csse.2022.019106

Abstract Timing speculative (TS) architecture is promising for improving the energy efficiency of microprocessors. Error recovery units, designed for tolerating occasional timing errors, have been used to support a wider range of voltage scaling, therefore to achieve a better energy efficiency. More specifically, the timing error rate, influenced mainly by data forwarding, is the bottleneck for voltage down-scaling in TS processors. In this paper, a new Timing Error Aware Register Allocation method is proposed. First, we designed the Dependency aware Interference Graph (DIG) construction to get the information of Read after Write (RAW) in programs. To build the construction, we get… More >