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Search Results (18)
  • Open Access

    ARTICLE

    Towards Cache-Assisted Hierarchical Detection for Real-Time Health Data Monitoring in IoHT

    Muhammad Tahir1,2,*, Mingchu Li1,2, Irfan Khan1,2, Salman A. Al Qahtani3, Rubia Fatima4, Javed Ali Khan5, Muhammad Shahid Anwar6

    CMC-Computers, Materials & Continua, Vol.77, No.2, pp. 2529-2544, 2023, DOI:10.32604/cmc.2023.042403

    Abstract Real-time health data monitoring is pivotal for bolstering road services’ safety, intelligence, and efficiency within the Internet of Health Things (IoHT) framework. Yet, delays in data retrieval can markedly hinder the efficacy of big data awareness detection systems. We advocate for a collaborative caching approach involving edge devices and cloud networks to combat this. This strategy is devised to streamline the data retrieval path, subsequently diminishing network strain. Crafting an adept cache processing scheme poses its own set of challenges, especially given the transient nature of monitoring data and the imperative for swift data transmission, intertwined with resource allocation tactics.… More >

  • Open Access

    ARTICLE

    Power Information System Database Cache Model Based on Deep Machine Learning

    Manjiang Xing*

    Intelligent Automation & Soft Computing, Vol.37, No.1, pp. 1081-1090, 2023, DOI:10.32604/iasc.2023.034750

    Abstract At present, the database cache model of power information system has problems such as slow running speed and low database hit rate. To this end, this paper proposes a database cache model for power information systems based on deep machine learning. The caching model includes program caching, Structured Query Language (SQL) preprocessing, and core caching modules. Among them, the method to improve the efficiency of the statement is to adjust operations such as multi-table joins and replacement keywords in the SQL optimizer. Build predictive models using boosted regression trees in the core caching module. Generate a series of regression tree… More >

  • Open Access

    ARTICLE

    Ether-IoT: A Realtime Lightweight and Scalable Blockchain-Enabled Cache Algorithm for IoT Access Control

    Hafiz Adnan Hussain*, Zulkefli Mansor, Zarina Shukur, Uzma Jafar

    CMC-Computers, Materials & Continua, Vol.75, No.2, pp. 3797-3815, 2023, DOI:10.32604/cmc.2023.034671

    Abstract Several unique characteristics of Internet of Things (IoT) devices, such as distributed deployment and limited storage, make it challenging for standard centralized access control systems to enable access control in today’s large-scale IoT ecosystem. To solve these challenges, this study presents an IoT access control system called Ether-IoT based on the Ethereum Blockchain (BC) infrastructure with Attribute-Based Access Control (ABAC). Access Contract (AC), Cache Contract (CC), Device Contract (DC), and Policy Contract (PC) are the four central smart contracts (SCs) that are included in the proposed system. CC offers a way to save user characteristics in a local cache system… More >

  • Open Access

    ARTICLE

    A Time Pattern-Based Intelligent Cache Optimization Policy on Korea Advanced Research Network

    Waleed Akbar, Afaq Muhammad, Wang-Cheol Song*

    Intelligent Automation & Soft Computing, Vol.36, No.3, pp. 3743-3759, 2023, DOI:10.32604/iasc.2023.036440

    Abstract Data is growing quickly due to a significant increase in social media applications. Today, billions of people use an enormous amount of data to access the Internet. The backbone network experiences a substantial load as a result of an increase in users. Users in the same region or company frequently ask for similar material, especially on social media platforms. The subsequent request for the same content can be satisfied from the edge if stored in proximity to the user. Applications that require relatively low latency can use Content Delivery Network (CDN) technology to meet their requirements. An edge and the… More >

  • Open Access

    ARTICLE

    Shared Cache Based on Content Addressable Memory in a Multi-Core Architecture

    Allam Abumwais*, Mahmoud Obaid

    CMC-Computers, Materials & Continua, Vol.74, No.3, pp. 4951-4963, 2023, DOI:10.32604/cmc.2023.032822

    Abstract Modern shared-memory multi-core processors typically have shared Level 2 (L2) or Level 3 (L3) caches. Cache bottlenecks and replacement strategies are the main problems of such architectures, where multiple cores try to access the shared cache simultaneously. The main problem in improving memory performance is the shared cache architecture and cache replacement. This paper documents the implementation of a Dual-Port Content Addressable Memory (DPCAM) and a modified Near-Far Access Replacement Algorithm (NFRA), which was previously proposed as a shared L2 cache layer in a multi-core processor. Standard Performance Evaluation Corporation (SPEC) Central Processing Unit (CPU) 2006 benchmark workloads are used… More >

  • Open Access

    ARTICLE

    Cache Memory Design for Single Bit Architecture with Different Sense Amplifiers

    Reeya Agrawal1,*, Anjan Kumar1, Salman A. AlQahtani2, Mashael Maashi3, Osamah Ibrahim Khalaf4, Theyazn H. H. Aldhyani5

    CMC-Computers, Materials & Continua, Vol.73, No.2, pp. 2313-2331, 2022, DOI:10.32604/cmc.2022.029019

    Abstract Most modern microprocessors have one or two levels of on-chip caches to make things run faster, but this is not always the case. Most of the time, these caches are made of static random access memory cells. They take up a lot of space on the chip and use a lot of electricity. A lot of the time, low power is more important than several aspects. This is true for phones and tablets. Cache memory design for single bit architecture consists of six transistors static random access memory cell, a circuit of write driver, and sense amplifiers (such as voltage… More >

  • Open Access

    ARTICLE

    A Dominating Set Routing Scheme for Adaptive Caching in Ad Hoc Network

    Raed Alsaqour1, Ammar Al-hamadani2, Maha Abdelhaq3,*, Joud Almeheimidy3

    Intelligent Automation & Soft Computing, Vol.32, No.3, pp. 1587-1603, 2022, DOI:10.32604/iasc.2022.021127

    Abstract Current efforts for providing an efficient dynamic source routing protocol (DSR) for use in multi-hop ad-hoc wireless are promising. This is since DSR has a unique characteristic in that it uses source routing, instead of relying on the routing table at each intermediate device. This study addresses the current challenges facing DSR protocol in terms of the dynamic changes of the route and how to update such changes into the route cache of the DSR. The challenges typically persist when a sudden route break occurs resulting in a delay in updating the new node location into the cache of the… More >

  • Open Access

    ARTICLE

    A DQN-Based Cache Strategy for Mobile Edge Networks

    Siyuan Sun1,*, Junhua Zhou2, Jiuxing Wen3, Yifei Wei1, Xiaojun Wang4

    CMC-Computers, Materials & Continua, Vol.71, No.2, pp. 3277-3291, 2022, DOI:10.32604/cmc.2022.020471

    Abstract The emerging mobile edge networks with content caching capability allows end users to receive information from adjacent edge servers directly instead of a centralized data warehouse, thus the network transmission delay and system throughput can be improved significantly. Since the duplicate content transmissions between edge network and remote cloud can be reduced, the appropriate caching strategy can also improve the system energy efficiency of mobile edge networks to a great extent. This paper focuses on how to improve the network energy efficiency and proposes an intelligent caching strategy according to the cached content distribution model for mobile edge networks based… More >

  • Open Access

    ARTICLE

    Dual-Port Content Addressable Memory for Cache Memory Applications

    Allam Abumwais1,*, Adil Amirjanov1, Kaan Uyar1, Mujahed Eleyat2

    CMC-Computers, Materials & Continua, Vol.70, No.3, pp. 4583-4597, 2022, DOI:10.32604/cmc.2022.020529

    Abstract Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed. This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory (DPCAM). In addition, it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm (NFRA) to reduce the cost overhead of the cache controller and improve the cache access latency. The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory. Moreover, it was shown… More >

  • Open Access

    ARTICLE

    ECC: Edge Collaborative Caching Strategy for Differentiated Services Load-Balancing

    Fang Liu1,*, Zhenyuan Zhang2, Zunfu Wang1, Yuting Xing3

    CMC-Computers, Materials & Continua, Vol.69, No.2, pp. 2045-2060, 2021, DOI:10.32604/cmc.2021.018303

    Abstract Due to the explosion of network data traffic and IoT devices, edge servers are overloaded and slow to respond to the massive volume of online requests. A large number of studies have shown that edge caching can solve this problem effectively. This paper proposes a distributed edge collaborative caching mechanism for Internet online request services scenario. It solves the problem of large average access delay caused by unbalanced load of edge servers, meets users’ differentiated service demands and improves user experience. In particular, the edge cache node selection algorithm is optimized, and a novel edge cache replacement strategy considering the… More >

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