Yi Zhang¹, Wenliang Zhu^1,*, Hanbin Wang¹, Chun Tian², Jiajun Zhou²

CMES-Computer Modeling in Engineering & Sciences, Vol.144, No.3, pp. 2873-2891, 2025, DOI:10.32604/cmes.2025.068951 - 30 September 2025

Abstract Aiming to address the challenge of directly measuring the real-time adhesion coefficient between wheels and rails, this paper proposes an online estimation algorithm for the adhesion coefficient based on parameter estimation. Firstly, a force analysis of the single-wheel pair model of the train is conducted to derive the calculation relationship for the wheel-rail adhesion coefficient in train dynamics. Then, an estimator based on parameter estimation is designed, and its stability is verified. This estimator is combined with the wheelset force analysis to estimate the wheel-rail adhesion coefficient. Finally, the approach is validated through joint simulations… More >

Ayoub Mhaouch^1,*, Wafa Gtifa², Turke Althobaiti³, Hamzah Faraj⁴, Mohsen Machhout¹

CMC-Computers, Materials & Continua, Vol.84, No.3, pp. 5637-5663, 2025, DOI:10.32604/cmc.2025.065525 - 30 July 2025

Abstract In medical imaging, accurate brain tumor classification in medical imaging requires real-time processing and efficient computation, making hardware acceleration essential. Field Programmable Gate Arrays (FPGAs) offer parallelism and reconfigurability, making them well-suited for such tasks. In this study, we propose a hardware-accelerated Convolutional Neural Network (CNN) for brain cancer classification, implemented on the PYNQ-Z2 FPGA. Our approach optimizes the first Conv2D layer using different numerical representations: 8-bit fixed-point (INT8), 16-bit fixed-point (FP16), and 32-bit fixed-point (FP32), while the remaining layers run on an ARM Cortex-A9 processor. Experimental results demonstrate that FPGA acceleration significantly outperforms the… More >

Go-Eun Woo, Sang-Bo Park, Gi-Tae Park, Muhammad Junaid, Hyung-Won Kim^*

CMC-Computers, Materials & Continua, Vol.84, No.2, pp. 3241-3257, 2025, DOI:10.32604/cmc.2025.063723 - 03 July 2025

Abstract On-device Artificial Intelligence (AI) accelerators capable of not only inference but also training neural network models are in increasing demand in the industrial AI field, where frequent retraining is crucial due to frequent production changes. Batch normalization (BN) is fundamental to training convolutional neural networks (CNNs), but its implementation in compact accelerator chips remains challenging due to computational complexity, particularly in calculating statistical parameters and gradients across mini-batches. Existing accelerator architectures either compromise the training accuracy of CNNs through approximations or require substantial computational resources, limiting their practical deployment. We present a hardware-optimized BN accelerator… More >

Borja Bordel Sánchez^1,*, Fernando Rodríguez-Sela¹, Ramón Alcarria², Tomás Robles¹

CMC-Computers, Materials & Continua, Vol.83, No.2, pp. 1821-1853, 2025, DOI:10.32604/cmc.2025.059012 - 16 April 2025

Abstract The Industry 4.0 revolution is characterized by distributed infrastructures where data must be continuously communicated between hardware nodes and cloud servers. Specific lightweight cryptosystems are needed to protect those links, as the hardware node tends to be resource-constrained. Then Pseudo Random Number Generators are employed to produce random keys, whose final behavior depends on the initial seed. To guarantee good mathematical behavior, most key generators need an unpredictable voltage signal as input. However, physical signals evolve slowly and have a significant autocorrelation, so they do not have enough entropy to support high-randomness seeds. Then, electronic… More >

Jingya Feng¹, Ying Zhao^2,*, Tao Ye¹, Wei Feng^3,*

CMC-Computers, Materials & Continua, Vol.83, No.1, pp. 1491-1507, 2025, DOI:10.32604/cmc.2025.059882 - 26 March 2025

Abstract The efficient implementation of the Advanced Encryption Standard (AES) is crucial for network data security. This paper presents novel hardware implementations of the AES S-box, a core component, using tower field representations and Boolean Satisfiability (SAT) solvers. Our research makes several significant contributions to the field. Firstly, we have optimized the GF() inversion, achieving a remarkable 31.35% area reduction (15.33 GE) compared to the best known implementations. Secondly, we have enhanced multiplication implementations for transformation matrices using a SAT-method based on local solutions. This approach has yielded notable improvements, such as a 22.22% reduction in More >

Zerong Tang, Tiecheng Song^*, Jing Hu

CMC-Computers, Materials & Continua, Vol.81, No.1, pp. 1835-1854, 2024, DOI:10.32604/cmc.2024.056983 - 15 October 2024

Abstract The Internet of Vehicles (IoV) will carry a large amount of security and privacy-related data, which makes the secure communication between the IoV terminals increasingly critical. This paper studies the joint beamforming for physical-layer security transmission in the coexistence of Vehicle-to-Infrastructure (V2I) and Vehicle-to-Vehicle (V2V) communication with Reconfigurable Intelligent Surface (RIS) assistance, taking into account hardware impairments. A communication model for physical-layer security transmission is established when the eavesdropping user is present and the base station antenna has hardware impairments assisted by RIS. Based on this model, we propose to maximize the V2I physical-layer security… More >

Ankitkumar Patel¹, Srivathsan Vasudevan^1,*, Satya Bulusu^2,*

CMC-Computers, Materials & Continua, Vol.80, No.3, pp. 3803-3818, 2024, DOI:10.32604/cmc.2024.052851 - 12 September 2024

Abstract Molecular Dynamics (MD) simulation for computing Interatomic Potential (IAP) is a very important High-Performance Computing (HPC) application. MD simulation on particles of experimental relevance takes huge computation time, despite using an expensive high-end server. Heterogeneous computing, a combination of the Field Programmable Gate Array (FPGA) and a computer, is proposed as a solution to compute MD simulation efficiently. In such heterogeneous computation, communication between FPGA and Computer is necessary. One such MD simulation, explained in the paper, is the (Artificial Neural Network) ANN-based IAP computation of gold (Au₁₄₇ & Au₃₀₉) nanoparticles. MD simulation calculates the forces… More >

Fangzhou He^1,3, Ke Ding^1,2, Dingjiang Yan³, Jie Li^3,*, Jiajun Wang^1,2, Mingzhe Chen^1,2

CMC-Computers, Materials & Continua, Vol.80, No.2, pp. 3021-3045, 2024, DOI:10.32604/cmc.2024.053632 - 15 August 2024

Abstract Massive computational complexity and memory requirement of artificial intelligence models impede their deployability on edge computing devices of the Internet of Things (IoT). While Power-of-Two (PoT) quantization is proposed to improve the efficiency for edge inference of Deep Neural Networks (DNNs), existing PoT schemes require a huge amount of bit-wise manipulation and have large memory overhead, and their efficiency is bounded by the bottleneck of computation latency and memory footprint. To tackle this challenge, we present an efficient inference approach on the basis of PoT quantization and model compression. An integer-only scalar PoT quantization (IOS-PoT)… More >

Mohamed Karray^1,*, Nesrine Triki^2,*, Mohamed Ksantini²

CMC-Computers, Materials & Continua, Vol.80, No.1, pp. 119-138, 2024, DOI:10.32604/cmc.2024.051562 - 18 July 2024

Abstract Advanced Driver Assistance Systems (ADAS) technologies can assist drivers or be part of automatic driving systems to support the driving process and improve the level of safety and comfort on the road. Traffic Sign Recognition System (TSRS) is one of the most important components of ADAS. Among the challenges with TSRS is being able to recognize road signs with the highest accuracy and the shortest processing time. Accordingly, this paper introduces a new real time methodology recognizing Speed Limit Signs based on a trio of developed modules. Firstly, the Speed Limit Detection (SLD) module uses… More >

Senjie Zhang^1,2, Jinbo Wang^2,*, Shan Zhou², Jingpei Wang^2,3, Zhenyong Zhang^4,*, Ruixue Wang²

CMC-Computers, Materials & Continua, Vol.78, No.1, pp. 1027-1047, 2024, DOI:10.32604/cmc.2023.046355 - 30 January 2024

Abstract The globalization of hardware designs and supply chains, as well as the integration of third-party intellectual property (IP) cores, has led to an increased focus from malicious attackers on computing hardware. However, existing defense or detection approaches often require additional circuitry to perform security verification, and are thus constrained by time and resource limitations. Considering the scale of actual engineering tasks and tight project schedules, it is usually difficult to implement designs for all modules in field programmable gate array (FPGA) circuits. Some studies have pointed out that the failure of key modules tends to… More >