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An FPGA Design for Real-Time Image Denoising

Ahmed Ben Atitallah*

Department of Electrical Engineering, Jouf University, Sakaka, Aljouf, Saudi Arabia

* Corresponding Author: Ahmed Ben Atitallah. Email: email

Computer Systems Science and Engineering 2022, 43(2), 803-816. https://doi.org/10.32604/csse.2022.024393

Abstract

The increasing use of images in miscellaneous applications such as medical image analysis and visual quality inspection has led to growing interest in image processing. However, images are often contaminated with noise which may corrupt any of the following image processing steps. Therefore, noise filtering is often a necessary preprocessing step for the most image processing applications. Thus, in this paper an optimized field-programmable gate array (FPGA) design is proposed to implement the adaptive vector directional distance filter (AVDDF) in hardware/software (HW/SW) codesign context for removing noise from the images in real-time. For that, the high-level synthesis (HLS) flow is used through the Xilinx Vivado HLS tool to reduce the design complexity of the HW part. The SW part is developed based on C/C++ programming language and executed on an advanced reduced instruction set computer (RISC) machines (ARM) Cortex-A53 processor. The communication between the SW and HW parts is achieved using the advanced extensible Interface stream (AXI-stream) interface to increase the data bandwidth. The experiment results on the Xilinx ZCU102 FPGA board show an improvement in processing time of the AVDDF filter by 98% for the HW/SW implementation relative to the SW implementation. This result is given for the same quality of image between the HW/SW and SW implementations in terms of the normalized color difference (NCD) and the peak signal to noise ratio (PSNR).

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APA Style
Atitallah, A.B. (2022). An FPGA design for real-time image denoising. Computer Systems Science and Engineering, 43(2), 803-816. https://doi.org/10.32604/csse.2022.024393
Vancouver Style
Atitallah AB. An FPGA design for real-time image denoising. Comput Syst Sci Eng. 2022;43(2):803-816 https://doi.org/10.32604/csse.2022.024393
IEEE Style
A.B. Atitallah, "An FPGA Design for Real-Time Image Denoising," Comput. Syst. Sci. Eng., vol. 43, no. 2, pp. 803-816. 2022. https://doi.org/10.32604/csse.2022.024393



cc This work is licensed under a Creative Commons Attribution 4.0 International License , which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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