Xiaoling Lai^1,2, Jian Zhang², Yangming Guo^1,*, Ting Ju², Qi Zhu², Guochang Zhou²

CMC-Computers, Materials & Continua, Vol.82, No.2, pp. 3091-3109, 2025, DOI:10.32604/cmc.2025.058688 - 17 February 2025

Abstract With the increase in the quantity and scale of Static Random-Access Memory Field Programmable Gate Arrays (SRAM-based FPGAs) for aerospace application, the volume of FPGA configuration bit files that must be stored has increased dramatically. The use of compression techniques for these bitstream files is emerging as a key strategy to alleviate the burden on storage resources. Due to the severe resource constraints of space-based electronics and the unique application environment, the simplicity, efficiency and robustness of the decompression circuitry is also a key design consideration. Through comparative analysis current bitstream file compression technologies, this… More >

Ankitkumar Patel¹, Srivathsan Vasudevan^1,*, Satya Bulusu^2,*

CMC-Computers, Materials & Continua, Vol.80, No.3, pp. 3803-3818, 2024, DOI:10.32604/cmc.2024.052851 - 12 September 2024

Abstract Molecular Dynamics (MD) simulation for computing Interatomic Potential (IAP) is a very important High-Performance Computing (HPC) application. MD simulation on particles of experimental relevance takes huge computation time, despite using an expensive high-end server. Heterogeneous computing, a combination of the Field Programmable Gate Array (FPGA) and a computer, is proposed as a solution to compute MD simulation efficiently. In such heterogeneous computation, communication between FPGA and Computer is necessary. One such MD simulation, explained in the paper, is the (Artificial Neural Network) ANN-based IAP computation of gold (Au₁₄₇ & Au₃₀₉) nanoparticles. MD simulation calculates the forces… More >

Senjie Zhang^1,2, Jinbo Wang^2,*, Shan Zhou², Jingpei Wang^2,3, Zhenyong Zhang^4,*, Ruixue Wang²

CMC-Computers, Materials & Continua, Vol.78, No.1, pp. 1027-1047, 2024, DOI:10.32604/cmc.2023.046355 - 30 January 2024

Abstract The globalization of hardware designs and supply chains, as well as the integration of third-party intellectual property (IP) cores, has led to an increased focus from malicious attackers on computing hardware. However, existing defense or detection approaches often require additional circuitry to perform security verification, and are thus constrained by time and resource limitations. Considering the scale of actual engineering tasks and tight project schedules, it is usually difficult to implement designs for all modules in field programmable gate array (FPGA) circuits. Some studies have pointed out that the failure of key modules tends to… More >

Tuo Ma, Zhiwei Li, Qingjiang Li^*, Haijun Liu, Zhongjin Zhao, Yinan Wang

CMC-Computers, Materials & Continua, Vol.77, No.3, pp. 3237-3263, 2023, DOI:10.32604/cmc.2023.045948 - 26 December 2023

Abstract With the continuous development of deep learning, Deep Convolutional Neural Network (DCNN) has attracted wide attention in the industry due to its high accuracy in image classification. Compared with other DCNN hardware deployment platforms, Field Programmable Gate Array (FPGA) has the advantages of being programmable, low power consumption, parallelism, and low cost. However, the enormous amount of calculation of DCNN and the limited logic capacity of FPGA restrict the energy efficiency of the DCNN accelerator. The traditional sequential sliding window method can improve the throughput of the DCNN accelerator by data multiplexing, but this method’s… More >

Turki M. Alanazi^*

Intelligent Automation & Soft Computing, Vol.37, No.2, pp. 1553-1568, 2023, DOI:10.32604/iasc.2023.039686 - 21 June 2023

Abstract Image processing is becoming more popular because images are being used increasingly in medical diagnosis, biometric monitoring, and character recognition. But these images are frequently contaminated with noise, which can corrupt subsequent image processing stages. Therefore, in this paper, we propose a novel nonlinear filter for removing “salt and pepper” impulsive noise from a complex color image. The new filter is called the Modified Vector Directional Filter (MVDF). The suggested method is based on the traditional Vector Directional Filter (VDF). However, before the candidate pixel is processed by the VDF, the MVDF employs a threshold… More >

Muhammad Rashid^1,*, Omar S. Sonbul¹, Muhammad Arif², Furqan Aziz Qureshi³, Saud. S. Alotaibi⁴, Mohammad H. Sinky¹

CMC-Computers, Materials & Continua, Vol.76, No.1, pp. 1009-1025, 2023, DOI:10.32604/cmc.2023.039901 - 08 June 2023

Abstract This work presents a flexible/unified hardware architecture of Elliptic-curve Cryptography (ECC) and PRESENT for cryptographic applications. The features of the proposed work are (i) computation of only the point multiplication operation of ECC over for a 163-bit key generation, (ii) execution of only the variant of an 80-bit PRESENT block cipher for data encryption & decryption and (iii) execution of point multiplication operation (ECC algorithm) along with the data encryption and decryption (PRESENT algorithm). To establish an area overhead for the flexible design, dedicated hardware architectures of ECC and PRESENT are implemented in the first More >

Mohamad Afendee Mohamed¹, Talal Bonny², Aceng Sambas³, Sundarapandian Vaidyanathan⁴, Wafaa Al Nassan², Sen Zhang⁵, Khaled Obaideen², Mustafa Mamat¹, Mohd Kamal Mohd Nawawi^6,*

CMC-Computers, Materials & Continua, Vol.75, No.3, pp. 5987-6006, 2023, DOI:10.32604/cmc.2023.035668 - 29 April 2023

Abstract In recent years, there are numerous studies on chaotic systems with special equilibrium curves having various shapes such as circle, butterfly, heart and apple. This paper describes a new 3-D chaotic dynamical system with a capsule-shaped equilibrium curve. The proposed chaotic system has two quadratic, two cubic and two quartic nonlinear terms. It is noted that the proposed chaotic system has a hidden attractor since it has an infinite number of equilibrium points. It is also established that the proposed chaotic system exhibits multi-stability with two coexisting chaotic attractors for the same parameter values but… More >

G. Venkatesan^1,*, N. Ramadass²

Computer Systems Science and Engineering, Vol.46, No.3, pp. 3979-3991, 2023, DOI:10.32604/csse.2023.031627 - 03 April 2023

Abstract Sensor networks are regularly sent to monitor certain physical properties that run in length from divisions of a second to many months or indeed several years. Nodes must advance their energy use for expanding network lifetime. The fault detection of the network node is very significant for guaranteeing the correctness of monitoring results. Due to different network resource constraints and malicious attacks, security assurance in wireless sensor networks has been a difficult task. The implementation of these features requires larger space due to distributed module. This research work proposes new sensor node architecture integrated with More >

Muhammad Rashid^*, Majid Alotaibi

CMC-Computers, Materials & Continua, Vol.74, No.3, pp. 6849-6865, 2023, DOI:10.32604/cmc.2023.032849 - 28 December 2022

Abstract We have proposed a flexible coprocessor key-authentication architecture for 80/112-bit security-related applications over field by employing Elliptic-curve Diffie Hellman (ECDH) protocol. Towards flexibility, a serial input/output interface is used to load/produce secret, public, and shared keys sequentially. Moreover, to reduce the hardware resources and to achieve a reasonable time for cryptographic computations, we have proposed a finite field digit-serial multiplier architecture using combined shift and accumulate techniques. Furthermore, two finite-state-machine controllers are used to perform efficient control functionalities. The proposed coprocessor architecture over and is programmed using Verilog and then implemented on Xilinx Virtex-7 FPGA More >

N. Sathiabama^1,*, S. Anila²

Computer Systems Science and Engineering, Vol.45, No.3, pp. 2705-2720, 2023, DOI:10.32604/csse.2023.025941 - 21 December 2022

Abstract Interconnected cells, Configurable Logic Blocks (CLBs), and input/output (I/O) pads are all present in every Field Programmable Gate Array (FPGA) structure. The interconnects are formed by the physical paths for connecting the blocks . The combinational and sequential circuits are used in the logic blocks to execute logical functions. The FPGA includes two different tests called interconnect testing and logical testing. Instead of using an additional circuitry, the Built-in-Self-Test (BIST) logic is coded into an FPGA, which is then reconfigured to perform its specific operation after the testing is completed. As a result, additional test… More >