Variational Graph Autoencoder–Based Timing-Driven Initialization Placement
Ziyi Ju1, Ping Yu1, Rui Song1, Tonglin Chen1,2,*
1 School of Computer Science and Technology, Fudan University, Shanghai, China
2 Fudan University-China Railway 24th Bureau Joint Laboratory for Intelligent Construction Engineering Technologies on Operational Railway Lines, The China Railway 24th Bureau Group Corporation Limited, Shanghai, China
* Corresponding Author: Tonglin Chen. Email: 
Computers, Materials & Continua https://doi.org/10.32604/cmc.2026.082060
Received 11 March 2026; Accepted 04 June 2026; Published online 18 June 2026
Abstract
In modern high-performance chip design, achieving timing closure is essential to design success. With the increasing scale and complexity of modern chips, timing-driven placement has become increasingly important. Traditional placement methods primarily focus on minimizing wirelength, but lack timing optimization, making it difficult to meet the strict timing closure requirements of modern designs. Therefore, developing an efficient timing-driven placement method has become a critical challenge in modern chip design. This paper presents a novel timing-driven placement framework that integrates a variational graph autoencoder (VGAE) with a nonlinear mixed-size placement optimizer. The framework identifies timing-violation paths through static timing analysis and dynamically adjusts interconnect weights based on pin-level timing slack, enabling the VGAE to generate an initial placement that prioritizes critical-path optimization. Experimental results on the ICCAD2015 benchmarks show that the proposed method achieves a 25.4% improvement in worst negative slack and a 18.1% improvement in total negative slack compared with DREAMPlace4.0. These results demonstrate its effectiveness in improving timing quality.
Keywords
Timing optimization; timing-driven placement; variational graph autoencoder; weight updating; nonlinear optimization
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