Submit

Login Login

Register Register

Home / Journals / CMC / Online First / doi:10.32604/cmc.2026.085065
Journal Menu
Special Issues
Table of Content

All issues

Online First

2026

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

Open Access

ARTICLE

Efficient Cryptographic Architectures for Edge AI and Real-Time Embedded Systems

Makhkamov Bakhtiyor Shukhratovich1, Akmalbek Abdusalomov1,2,3,4, Akhmedova Nodira Aminjanovna1, Botirov Sokhibjon Rustam Ugli1, Jasur Sevinov2,5, Alpamis Kutlimuratov6, Boburjon Vafoev7, Yodgorkhon Ilkhamova7, Young Im Cho8,*
1 Department of Computer Systems/Physics, Tashkent University of Information Technologies Named after Muhammad Al-Khwarizmi, Tashkent, Uzbekistan
2 Department of Information Processing and Control Systems, Tashkent State Technical University, Tashkent, Uzbekistan
3 Department of Electronics and Instrumentation, Fergana State Technical University, Fergana, Uzbekistan
4 Department of International Scientific Journals and Rankings, Alfraganus University, Tashkent, Uzbekistan
5 Department of Computer Engineering, University of Tashkent for Applied Sciences, Tashkent, Uzbekistan
6 Department of Applied Informatics, Kimyo International University in Tashkent, Tashkent, Uzbekistan
7 Department of Digital Economy, Tashkent State University of Economics, Tashkent, Uzbekistan
8 Department of Computer Engineering, Gachon University, Seongnam-si, Gyeonggi-Do, Republic of Korea
* Corresponding Author: Young Im Cho. Email: email

Computers, Materials & Continua https://doi.org/10.32604/cmc.2026.085065

Received 06 May 2026; Accepted 10 August 2026; Published online 10 September 2026

Abstract

This paper presents field-programmable gate array (FPGA)-based engineering optimizations of the Ascon lightweight cryptographic algorithm, targeting real-time edge AI and embedded systems. The work systematically evaluates how established design strategies, such as selective round unrolling and pipelined permutation stages, scale across heterogeneous FPGA platforms. Two architectures are explored, each optimized for different design objectives, including throughput (TP), latency, and hardware efficiency. The designs are implemented on two FPGA families, Xilinx Kintex UltraScale and the 7-Series Spartan, to evaluate scalability across both high-performance and resource-constrained platforms. Experimental results show that selective round unrolling in Architecture 2 achieves the highest TP, reaching 624.57 Mb/s on UltraScale and 377.78 Mb/s on Spartan-7, while Architecture 1 provides the lowest LUT utilization, requiring as few as 1804 LUTs. Throughput-to-area ratio analysis reveals platform-dependent efficiency, with Architecture 2 performing best on UltraScale and Architecture 1 on Spartan-7. Application mapping demonstrates suitability across smart surveillance, autonomous systems, and embedded inference nodes. The results indicate that lightweight Ascon architectures can be suitable for diverse edge environments, based on their measured TP, latency, and area characteristics.

Keywords

Lightweight cryptography; FPGA architectures; edge AI systems

  • 165

    View

  • 29

    Download

  • 1

    Like

Related articles
Copyright© 2026 Tech Science Press
© 1997-2026 TSP (Henderson, USA) unless otherwise stated

Share Link